Ultra-Thin Wafer-Level Chip Scale Packaging
SoP-TM™, the industry’s first wafer level CSP fully protected process has been released for customer use. The unique process features polyimide encasement on all 6 sides of the die. New product developments utilizing ultra-thin and/or flexible electronics have suffered for lack of the test chips needed to develop next generation advanced manufacturing processes. Thin, bare silicon is not sufficient for this requirement.
Full function ICs are difficult to easily test and can be expensive to use for process development. Many new applications need chip scale packaged (CSP) ICs with full chip encapsulation for protection against damage and environmental exposure. American Semiconductor has released a new line-up of SoP-TM™ (6 side protected) CSP Test Chips that are designed for use in adoption of the new packaging technology.
These ultra-thin test chips include a variety of on-chip interconnects that enable quick and efficient testing of new assembly process capability. See the new Test Chips here.
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